1. Field of the Invention
The present invention relates to the field of the fabrication of silicided gate devices by means of a CMP integration scheme.
2. Description of the Related Technology
CMP is a method of removing layers of solid by chemical-mechanical polishing carried out for the purpose of surface planarization. In a chemical-mechanical polishing (CMP) scheme after the planarization step, the material (e.g. oxide) covering the wafer is thinner on top of smaller structures (t2) than on top of larger structures (t1), as illustrated in FIG. 1. This is a characteristic feature of a CMP process. This CMP non-uniformity within-die and also within-wafer has an impact on the dry etch process that clears the oxide from the top of the poly-Si gates, while leaving the source/drain (S/D) areas covered by oxide. Indeed, to guarantee that oxide on top of all gate electrodes (small and large) is removed (which constitutes an essential condition to (fully) silicide the gates later on), an over-etch time has to be applied. The higher the non-uniformity values, the longer the over-etch time needs to be. This puts stricter constraints on the dry etch process, since a very high etch rate selectivity of the gate electrode material (e.g. poly-Si) vs. that of the material (e.g. oxide) covering the devices is then required. If, for example, there is still an oxide layer of a certain thickness on top of some gate electrodes, while some other devices are already oxide cleared out, then the dry etch selectivity towards the gate electrode should be very high to ensure that all gate electrodes end up with the same final height.
FIG. 1 schematically represents the process flow showing the CMP non-uniformity problem encountered in the prior art. On a semiconductor substrate (10), shallow trench isolation (STI) regions (11) are defined, followed by gate stack patterning. Gate structures with different lengths were defined as shown in FIG. 1a: (I) small gate; (II) large gate. The conventional gate stack consists of a thin gate dielectric layer (12), a gate electrode (13) and an additional layer (14). After gate patterning, spacers (15) definition and silicidation of the source and drain regions (16), a material (17) is deposited in order to planarize the structures prior to the chemical-mechanical-polishing (CMP). After the CMP, the non-uniformity of the remaining material is illustrated by the different values of the thickness on top of the large gates (t1) and the small gates (t2), with t1>t2 as shown in FIG. 1a. FIG. 1b shows schematically the exposed gate electrode on the small gate (I) after the oxide etch-back step. During the over-etch step need to clear out the material (17) and the additional layer (14) from the larger gate structures, the gate electrode (13) from the small gates (I) is partially consumed, whereas on the large gates (II) the initial telectrode thickness is still present as illustrated in FIG. 1c. 
The CMP non-uniformity could possibly be improved with the use of a liner (stop CMP liner). The problem with implementing this alternative approach is in the choice of the material(s) to use as liner, such that the spacers integrity is not compromised and the process complexity is not increased (as if a liner with multiple layers were chosen). A nitride stop CMP liner as disclosed by Wong et al. in U.S. Pat. No. 5,731,239 does not completely solve the non-uniformity problem after CMP and limits the choice of spacer material to oxide. In this case, if nitride spacers were used, their integrity would be affected by the liner removal step.
It is thus desirable to provide a method for controlling the height of gate electrodes in a silicidation process.